Vlsi Architecture Of Cdma Rake Receiver With Low Hardware Complexity For Pcs

In this paper, we propose a VLSI architecture of CDMA rake receiver which consists of a searcher and three fingers having some shared hardware blocks to reduce the hardware complexity. The proposed rake receiver suitable for IS-95 based CDMA PCS system was designed using VHDL and it contains about 30K logic gates. We also implemented our system on FPGA chips and it was successfully tested.