High throughput FPGA implementation of Reed-Solomon Encoder for Space Data Systems

Reed Solomon code is one of the most powerful channel code that provide high bit error tolerance with good coding gain and low overheads. Reed Solomon RS(255,239) Encoder along with shortened configuration have been developed using VHDL that is fully compatible to Consultative Committee for Space Data Systems(CCSDS) standard. The development being at register transfer level can be ported to any FPGA and ASIC. This development provides ready to use solution of high throughput Reed Solomon encoder for CCSDS recommended configuration. The encoder design is optimized to supports high data rate with minimal resource utilization. The Register Transfer Level (RTL) VHDL design of RS encoder is developed, simulated and implemented in Actel ProASIC 3E FPGA. The paper give brief overview of RS encoder related to design and performance followed by development results of simulation and hardware implementation.