Low Power Operation of a Vertical Cavity Transistor Laser via the Reduction of Collector Offset Voltage

Data are presented on low-power operation in a vertical cavity transistor laser via reduced collector offset voltage by placing the emitter contact on the top of four pairs of the GaAs/AlGaAs DBR to reduce emitter resistance and subsequently depositing 11 SiO
₂
/TiO
₂
DBR pairs to improve cavity quality. Consequently, the device demonstrates a reduced collector offset voltage of 1.65 V and a low-power dissipation of 6.32 mW under laser operation.