Robustness study and CNFET realization of optimal logic circuit for ultralow power applications

Subthreshold circuits have emerged as a strong alternative for ultralow power applications. This paper first investigates the output levels of the NAND and NOR gates in subthreshold region of operation and carries out analysis on various design metrics. Analysis mainly consists of estimation of propagation delay (t_p) and power-delay product (PDP) as a function of supply voltage. It also performs variability analysis of performance metrics such as t_p and PDP to determine the robustness of the NAND and NOR circuits in subthreshold regime. Four logic styles were carefully analyzed with a simulation test bench on HSPICE at 16-nm technology. The objective of the analysis is to identify suitable logic family with best performance and least variability with respect to t_p and PDP under subthreshold condition, where circuits are susceptible to process, voltage and temperature (PVT) variations. Finally, optimal NAND and NOR circuit was implemented using CNFET technology to achieve even improved results in terms of propagation delay and PDP.