HDL based implementation of N×N bit-serial multiplier

The paper proposes a systematic design methodology for bit-serial multiplication. The proposed approach is a modified method for performing traditional multiplication. This paper presents a general technique for N×N bit-serial multiplication used in signal processing. HDL implementation and simulation of 4×4 bit-serial multiplier is discussed. Synthesis is performed using Xilinx ISE with Virtex-4 ML402 FPGA board.