Packaging Very Fast Switching Semiconductors

The switching speed of power semiconductors has reached levels where conventional semiconductor packages limit the achievable performance due to parasitic inductance and capacitance. Designing these parasitics intentionally is the key to overcome this speed limit. This paper gives an overview on relevant parasitic effects in semiconductor properties, package and switching cell design. A module with extremely low dc link inductance is built up using a newly developed packaging technology. The experimental results lead to a proposal for next step in package design for fast switching and minimizing EMI generation.