Layering processes and their applications in silicon microelectronics

Historically, both the cost reduction and the performance improvement of silicon microelectronic devices are unparalleled. In addition, the pervasiveness of silicon-based integrated circuits (ICs) in electronic systems continues as the industry moves into the gigachip age with giga-scale integration (GSI). Metal-oxide silicon field-effect transistors (MOSFETs) are used in circuits ranging from memories to microprocessors to custom logic circuits for such functions as echo cancellation, voice recognition, data encryption, and high-definition television. Indeed, the power of silicon circuits is limited only by their size or the level of integration. One limiting factor in the fabrication of submicron devices is the process stress budget. A complete rethinking of both the stress budget (reduction and accommodation) and microstructural control (grain size and distribution) is vital to maintaining dimensional integrity against typical critical fabrication process steps, such as polysilicon or metal deposition. This paper discusses the impact of stress accommodation achieved through layering in polysilicon and metal interconnect systems in silicon microelectronics.