Full channel simulation for high speed 2.5D package with silicon interposer

In this paper, a full channel simulation model of interposer and organic substrate is established. The TSV (through silicon via) interposer provides high-bandwidth, low-latency interconnection to accomplish higher performance and reach smaller size of the semiconductor devices. For 2.5D packaging, it's extremely necessary and pressing to estimate the electrical property and optimize the structure for TSV interposer. The model of ground-signal-signal-ground (GSSG) coplanar lines of differential pair in redistribution layer (RDL) on the interposer with TSVs is simulated by Ansoft's HFSS. In addition, another strip line model of this differential pair in organic substrate is simulated. Then a co-simulation method of the full channel is proposed utilizing Agilent's ADS. By using the simulation approach, the signal quality of this channel is presented and some signal integrity (SI) issues are discussed by analyzing the S-parameter and eye diagram.