Delamination analysis and reliability design for CMOS image sensors packages

Through-silicon via (TSV) technology known as the core of the next generation of 3D integration has drawn more and more attention. However, due to its high cost and yield problems, it has not been used widely. Nevertheless, TSV is becoming a main stream interconnect method for CIS (CMOS image sensors) packaging. In order to assess the reliability behavior of typical CMOS image sensor such as delamination during CIS packaging and reliability testing, CSP packages are subjected to JEDEC reliability test to identify the failure modes and failure locations. According to the subsequent cross-section analysis, delamination occurs between the bonding attach and oxide layer. The glass crack after reliability test is observed, the crack propagates from the interface between the glass and cavity wall into the interior of the glass. Regarding the experimental results, a plane strain finite element model (FEM) is established to study the underlying mechanisms of reliability problems. According to the FEM results, the maximum shear stress in cavity wall occurs at the outside interface between cavity wall and the glass. The maximum shear stress in bonding attach occurs at the outside interface between the bonding attach and oxide layer. Besides, the maximum stress occurs in the low-temperature phase, which is correlated well with the SEM results. Based on the FEM analysis, the influence of geometric parameters such as the height and width of cavity wall, the thickness of the backside SMF, the thickness of silicon are also investigated to develop the guidelines for CIS packaging design.