On-chip static vs. dynamic routing for feed forward neural networks on multicore neuromorphic architectures

With processor reliability and power limiting the performance of future computing systems, interest in multicore neuromorphic architectures is increasing. These architectures require on-chip routing networks to enable cores to communicate neural outputs with each other. In this study we examine two routing approaches for large multicore feed forward neural network accelerators: static and dynamic. Models are developed to determine routing resources for 2D mesh interconnection topologies. Detailed analysis of power, area, and link utilization are carried out for several architecture options. In almost all cases, static routing is significantly more efficient than dynamic routing, requiring both lower area and power.