FPGA implementation of a fetal heart rate measuring system

Labor during pregnancy is an inherently dangerous life event for a live fetus and its mother. Non-invasive method of Fetal Heart Rate (FHR) measuring system helps to reduce Infant Mortality Rate (IMR) by continuous monitoring of the fetus heart rate. In this paper real-time implementation of a FHR measuring system has been developed using Xilinx Spartan-6 FPGA device, which can calculate the fetus heart rate and display ECG signal through HDMI port. In FHR extraction of the cleaned fetal ECG signal from the maternal ECG is the main challenge. In our proposed work Least Mean Square (LMS) adaptive filter has been used as the adaptive noise canceller along with dynamic thresholding technique for de-noising the fetus ECG signal and helps to achieve 88% accuracy in the proposed FHR system. FPGA implementation of the FHR system consumes 7.8K slices and can achieve sampling frequency of 80 MHz while implemented on XC6SLX45-3CSG484 FPGA device. The comparison results show that our proposed design is more efficient than the literature reported earlier.