Real-time efficient FPGA implementation of aes algorithm

An efficient optimized area and speed FPGA implementation for the Advanced Encryption Standard is proposed in this paper. The iterative looping method is adopted with multistage sub-pipelining architecture to achieve a 1.33 Gbps throughput for the AES-128 bit Encryption process. The proposed design operates at 425 MHz with 303 CLB slices on a Xilinx Virtex-5 XC5VLX50 FPGA Device. For real-time hardware evaluation, an end-user Java based application is developed. The software application is linked to the hardware design through the Xilinx MicroBlaze soft processor core.