The study of backside TSV reveal process by direct Si/Cu grinding and polishing

Despite the fact that manufacturing processes of through silicon via (TSV) have achieved great progresses, the backside via reveal process is still challenging and costly. The simplest TSV reveal method is using backside grinding (BG) and chemical mechanical polishing (CMP), by which the vias are revealed by CMP directly after wafer thinning with BG. However this method is not well accepted due to the Cu contamination concern. From the application point of view, if the Cu contamination is restrained in pretty low level with process optimization, it may be still possible to be applied to achieve the simple and economical process, especially for 2.5D interposer manufacturing which is more tolerant with Cu contamination. In this work, very low contamination level-copper atoms (lower than 0.000001%) were got in backside wafer surface after CMP of TSV vias, which is good enough for interposer or even 3DIC application.