Hardware implementation of the IDEA NXT crypto-algorithm

This paper introduces a novel hardware implementation of the IDEA NXT encryption algorithm resistant to attacks, and proposes a strategy for testing the implementation on an Altera DE2 FPGA. The proposed design is analysed with respect to execution time and throughput, revealing its effectiveness in comparison to conventional approaches. Also, its performance in terms of execution time and throughput is presented by comparison to the DES, IDEA and AES cryptographic algorithms, which have been extensively used in the past few decades, and also to other implementations of the NXT algorithm previously developed. The IDEA NXT crypto-algorithm surfaced only a few years ago and little work was done so far to prove its theoretical strengths or to bring improvements, and that is what this study tries to cover.