ArISE: Aging-aware instruction set encoding for lifetime improvement

Microprocessors fabricated at nanoscale nodes are exposed to accelerated transistor aging due to Bias Temperature Instability and Hot Carrier Injection. As a result, device delays increase over time reducing the Mean Time To Failure (MTTF) of the processor. To address this challenge, many (micro)-architectural techniques target the execution stage of the instruction pipeline, as this one is typically most critical. However, also the decoding stages can become aging-critical and limit the microprocessor lifetime, as we will show in this work. In this paper, we propose a novel aging-aware instruction set encoding methodology (ArISE), that improves the instruction encoding iteratively using a heuristic algorithm. Our experimental results show that MTTF of the decoding stages can be improved by 1.93x with negligible implementation costs.