Architecture of pipelined MBISTs and its configuration in complex SoC

In addressing the problem of area overhead, physical routing and timing management between memory built-in self-tests (MBISTs) controllers with hundreds of embedded memories in system on Chip (SoC), various approaches have been proposed. In addressing these problems, MBISTs structure and architectural design should be efficiently determined in detail so that the problems associated with the issues mentioned can be addressed. In the present paper, the inclusion of pipeline registers in MBIST is done automatically at the RTL level, and there are a number of measures discussed to produce a suitable structure for SoC designs. In order to test the 150 embedded memories in the WiMAX SoC as a case study, a total of 20 pipelined MBISTs are designed. MBIST is allocated by reference to its frequency, location, and type of memories. This paper presents the methodology to propose suitable architecture for WiMAX SoC with 20 MBIST controllers. All 20 MBISTs were synthesized together with a gate level netlist of WiMAX SoC using 90nm process technology. Results show a reduction in terms of area by about 3953 µm2, net switching power about 3 mW, and simulation time of about 3689 µs compared to the first proposed architecture.