Simplified representation of the LLR messages in the check node processor for NB-LDPC decoder

Non-Binary Low Density Parity Check Codes (NB-LDPC) are nowadays considered as a potential competitor of both binary LDPC and convolutional Turbo Codes, mainly when codes with short and moderate codeword lengths are used. The decoding process of these codes suffers from a high computational complexity which necessitates a high memory requirements to store the intrinsic and extrinsic Likelihood Ratio (LLR) messages. This paper addresses a simplified and efficient coding technique of the binary words carrying the LLR values by storing the difference of two consecutive LLRs instead of the entire values in the Check Node (CN) processor of NB-LDPC Decoder. A combined approach mixing two techniques: partial truncation and 2-bit coding technique leading to a memory reduction of 38 % is also presented. The Monte Carlo simulation results show that the proposed LLR representation schemes do not introduce a significant performance loss of the code.