A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits

Increasing design complexity coupled with new design and manufacturing techniques being used for modern integrate circuits is creating challenges for test environment. The goal of system-on chip (SoC) test scheduling has always been to reduce test application time. Added design constraints for SoC environment are making this scheduling more difficult. This difficulty is increased by manufacturing techniques like 3D stacked integrated circuits. Traditional test schedules for 3D stacked ICs can be either prohibitively long or may not exist without resorting to test partitioning. Partitioning methods proposed in literature have been ad hoc or simplistic. This paper presents a test partitioning method specifically designed for thermally constrained tests for the purpose of reducing test application time of 3D stacked integrated circuits under temperature constraint. The efficiency of the method is demonstrated by comparing it to the ad hoc methods previously investigated in the literature.