Peak-Efficiency Detection and Peak-Efficiency Tracking Algorithm for Switched-Mode DC–DC Power Converters

In this paper, the system allowing to detect the peak-efficiency point of the periodically switching MOS power transistor is presented. The use of this system concerns namely the integrated dc–dc converters, charge pumps, class-E amplifiers, or isolated MOSFET power switches. Information about the peak-efficiency point position can be used to modify the power-switch operating conditions, which allows us to obtain the maximal available power-efficiency for a given operating point. The algorithm of the peak-efficiency tracking is developed here on the example of integrated 3.2 MHz step-down (buck) 5-A dc–dc converter. In this example, sizes of NMOS and PMOS power transistors are adjusted “on the fly,” in order to obtain the highest possible efficiency. In particular, power efficiency is optimized for the output current $I_{\rm OUT}$ , battery and output voltages $V_{\rm BAT}$ and $V_{\rm OUT}$, switching frequency $f_{\rm SW}$, temperature, and process variations. The principle of the method relies on the balancing of the Joule heat energy dissipated on the resistive elements, and energy dissipated during the charging process of the transistors’ driving capacitances. As the result of the peak-efficiency tracking algorithm, the flat efficiency curve is obtained in a wide current range.