A configurable CMOS voltage DAC for multichannel detector systems

A CMOS voltage DAC has been developed for integration into multiple front-end electronics ASICs associated with the PHENIX detector located at the RHIC accelerator of Brookhaven National Laboratory. The topology allows wide-range output programmability by selection of an offset voltage and on-chip resistor and transistor sizing. The DAC is trimless and requires no external components, making it ideal for highly integrated collider detector systems. Errors associated with on-chip bias are minimized using a topology that implements a ratiometric relationship which compensates for absolute resistance value changes and is limited only by errors in the on-chip matching of MOSFETs and resistive devices. Temperature-induced errors associated with the integrated resistors are also minimized by the circuit topology and monolithic construction. All reference voltages and currents are derived using a single regulated voltage supply. This paper presents the general DAC architecture and design method, discusses on-chip matching issues and tradeoffs associated with device sizing and monolithic layout, and presents measured performance of various gate length DACs fabricated in a 1.2 /spl mu/m CMOS process including integral nonlinearity, differential nonlinearity, and slope and offset errors.