Signed fixed-point multiplier for DSP using vertically and crosswise algorithm

Multiplication is an important function in arithmetic operations. A CPU devotes a considerable amount of processing time in performing arithmetic operations. Multiplication requires substantially more hardware resources and processing time than addition and subtraction. Along with the speed its precision also plays a major role. Floating point multipliers provide required precision and they tend to consume more silicon area and are relatively slower compared to fixed-point multipliers. We propose a method for fast-fixed point signed multiplication based on Urdhava Tiryakbhyam method of Vedic mathematics. The multiplier architecture is based on Vertical and Crosswise structure of Vedic Mathematics. It generates all partial products and their sum in one step. This gives chances for modular design where smaller block can be used to design the bigger one. Design complexity gets reduced for inputs of larger number of bits and modularity gets increased. To further enhance the speed of the Urdhava Tiryakbhyam multiplier the adder blocks in the multiplier are implemented as carry save adders. The Verilog HDL coding is done for 16 bit (Q15) and 32 bit (Q31) fixed-point multiplier and synthesized and simulated using Xilinx XST and ISIM version 14.1.