A 1 V 0.9 mW at 100 MHz 2 k/spl times/16 b SRAM utilizing a half-swing pulsed-decoder and write-bus architecture in 0.25 /spl mu/m dual-Vt CMOS

The main limitation resulting from reducing signal swings is reduction in gate overdrive at the receiving transistor leading to delay penalty. This design overcomes this using positive and negative half-swing signals on high-capacitance predecode lines so active decode circuits see a full gate-overdrive, while reducing decoder power. The half-Vdd supply is generated internally with high efficiency using charge-recycling between positive and negative half-swing signals. SRAM architecture and decoder organization are described.