Nanometer CMOS from a mixed-signal/RF perspective

The demise of mixed-signal and RF circuit design in nanometer CMOS technologies was predicted, analyzed and well documented since the advent of 65nm technologies. [1-3]. Poor device matching, low intrinsic device gains, gate leakage, nonideal and poor quality passives, and myriad reliability constraints, such as electromigration and voltage limitations, have been identified as potential barriers to continued mixed-signal and RF embedded design. Not surprisingly, most of these problems also significantly impact logic gate and memory design. Many design techniques have been proposed to address these issues. The most prominent of these, with the declining cost and improving performance of logic gates, is the use of digital signal processing as a standard practice to correct for nonideal circuit properties such as mismatch, distortion and even noise. This practice has led to significant innovation on many levels, from the direct calibration of active and passive devices [4-8], to complete rearchitecting of entire systems [9-10] to move the analog/digital boundary closer to the inputs. The ongoing challenge is: given exponentially rising manufacturing costs, can continual product-level performance advances be achieved in a cost-competitive way?