GaP source-drain SOI 1T-DRAM: Solving the key technological challenges

Silicon based capacitorless 1-Transistor DRAM [1] has been persuaded as an alternative DRAM structure over the last decade, though the retention time has not improved enough to allow large array implementation. With scaling of the transistor dimension, the deficiency of the retention time becomes more prominent due to shortage of channel volume to store the charge. To improve the retention time and scalability, we have proposed gallium phosphide (GaP) source-drain on SOI substrate [2]. Figure 1 shows the basic device structure with SOI substrate and GaP-SD. Fig. 2 shows bandoffset between GaP and Si. Since most of the bandoffset occurs at the valence band, GaP-SD provides a very effective way to store and confine more holes effectively inside the channel for a longer amount of time. Figure 3 shows the basic BJT latch up [4] characteristics used for programing of GaP-SD and Si-SD devices at 30nm gate length. Even though both the devices have same body thickness, the achievable threshold voltage shift in GaP-SD device is much higher than the Si-SD device. Due to the incapability of storing enough charge, Si-SD 1T-DRAM is not usable at these nodes. On the other hand, as shown in Figure 4, GaP-SD 1T-DRAM can be scaled to even 20nm technology node satisfying the ITRS requirement of retention time of 64ms at 85°C. Table 1 shows the optimized device dimensions for 30nm and 20nm gate length along with the corresponding retention time.