Utilising advanced packaging technologies to enable smaller, more efficient GaN power devices

A new generation of Power chips, utilising GaN technologies, are emerging that need to address a number of more fundamental packaging issues that are pushing the package boundaries. To ensure that these new devices meet the need to be “smaller, faster, cheaper” as driven by the emerging applications in switch mode power supplies (SMPS), motor control, energy conversion and health management systems, the packaging process has adopted novel advanced packaging features, developed primarily for the generic high speed digital Semiconductor ‘chip’ industry. The device package performance is a significant factor and has an important role in solving system requirement challenges, in protecting the chip from environmental influences, enabling testing and utilizing standard processes to mount it onto a PCB. It is also a means of providing improved lifetime and reliability by enabling additional thermal management, current carrying capability and high voltage isolation. This presentation shows how the devices benefit from new technologies such as 3D and through silicon via that are emerging as “advanced” packaging and how these have been utilised to meet the thermal and electrical needs of the devices. The novel methods of interconnection, chip bumping and flip chip processes are detailed and the reasons for choices of assembly materials reviewed.