Enhanced linearity of CMOS power amplifier using adaptive common gate bias control

This paper presents a fully-integrated linear CMOS power amplifier (PA) with an adaptive gate bias circuit in Common-Gate (CG) amplifiers. The bias circuit is proposed to achieve a high linearity with deep class-AB biasing of Common-Source (CS) stage. The proposed single stage PA including the bias circuit is fabricated using 0.18-μm RF CMOS technology. The adaptive gate bias circuit improves the evolved universal terrestrial radio access adjacent channel leakage ratio (ACLR_E-UTRA) about 7 dB at a mid power region and 2.5 dB at a high power over a constant bias for the same LTE signal.