Low power microprocessors for comparative study on bus architecture and multiplexer architecture

Decreasing capacitance of bus lines is one of the effective ways to reduce whole power dissipation of LSIs. In this paper we compare microprocessors designed based on a bus architecture and a multiplexer architecture in terms of power dissipation and delay time. Through implementation of a test chip, the multiplexer architecture is effective to reduce power dissipation by about 30%.