A low phase noise 24/77 GHz dual-band sub-sampling PLL for automotive radar applications in 65 nm CMOS technology

A low phase noise 24/77 GHz dual-band subsampling PLL with a dual-band VCO is presented. Implemented in 65 nm CMOS technology, the proposed PLL occupies an area of 900 μm × 550 μm. The measured phase noise is -120.0 and -108.5 dBc/Hz at 1 MHz offset in 24 and 77 GHz modes respectively. With 1.3 V supply, the power consumption is 26.4 and 31.5 mW for 24 and 77 GHz modes respectively. Compared with other state-of-the-art works, the proposed PLL has the best phase noise performance among all of reported PLLs for automotive radar applications.