On upsizing length and noise margins

This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to operate over the whole voltage range. The improvements are: (i) calculating the threshold voltage (V
_th
) exactly (leading to exact L's); (ii) more accurate SNM estimations (using the maximum square method); (iii) sizing the widths for single input transitions. Simulations for INV, NAND-2, and NOR-2 show that V
_th
and L change by ~2%, while SNM's increase by ~30% with power and energy being reduced ~10× and ~20× respectively.