Discovering novel digital circuits using evolutionary techniques

Modern FPGAs provide a platform for implementation of uncommitted logic arrays which are also, in many cases, reconfigurable. Whilst this allows circuit functionality to be changed in time, it also provides a convenient environment in which to encourage the direct evolution (using genetic algorithms) of those circuit solutions themselves. In this paper we describe experiments which examine the possibility of evolving simple arithmetic and mathematical circuits. We show that it is possible to evolve both conventional cellular designs-such as ripple-carry adders-and also very novel solutions which are suitable for implementation on arrays such as Xilinx 6000 series FPGAs. We also discuss the evolutionary models that are used to achieve this: evolving network connection lists, and then refining to produce a closer simulation of the actual internal structure of the Xilinx architecture. We then go on to examine and discuss the possibility of evolving mathematical functions such as the square-root directly in combinational logic.