Simulator Implementation and Performance Study of a Polymorphous Array Computer

This paper reports the implementation of a simulation platform and the performance study for the PAAG array processor. PAAG is a novel, polymorphous array architecture that is capable of supporting a dynamic mixture of data parallel computation DLP), thread level parallel computation (TLP), and instruction level parallel computation (ILP). Simulation experiments have been conducted on the simulation platform and results are reported here. This confirms that PAAG is able to achieve satisfactory performance while running a mixture of data parallel, thread parallel and instruction level program segments.