TxSnoop: Power-Aware Transactional Snoop

Transactional Memory (TM) is a promising alternative to the lock-based programming for Chip Multiprocessors (CMPs). Hardware Transactional Memory (HTM) exploits hardware to implement transactions and so is faster than Software Transactional Memory (STM). HTMs rely on cache coherence protocol to detect conflicts and maintain consistency of transactional data. If two transactions access the same transactional memory address, and at least one of them writes to the address, the cache coherence protocol guarantees that only one transaction proceeds and the other one aborts. We found that a significant portion of cache snoops in HTMs is unnecessary and wastes power of interconnect and caches. In addition, many of these cache snoops happen in a coarse region. To improve power of HTMs, we propose TxSnoop, a profiling-based snoop mechanism which reduces needless snoops. We extended the Gem5 simulator to model HTM and evaluate TXSnoop. Our simulation results show that TxSnoop is effective and reduces power of interconnect and cache snoops up to 64% and 63%, respectively.