Fast and accurate power annotated simulation: Application to a many-core architecture

Power consumption is crucial in embedded systems, mainly because of the limited battery capacity and the problem of heat dissipation. The energy efficiency of System-on-Chips (SoCs) is optimized at both hardware and software level using simulation platforms. The challenge of these platforms lies in the tradeoff between accuracy and simulation speed for early architecture exploration and HW/SW validation. In the context of many-core systems in which heavy software stacks are executed, fast simulation platforms are required. In this paper, we present our power modeling approach of a complex many-core system to estimate the power consumption of software applications executed on it. We propose in particular a light and accurate power model for VLIW processors, as this kind of processor is commonly used in such systems. The power estimator we set up is part of a practical power characterization framework fully automated that includes low level simulations which are then used to back-annotate fast simulation models. Our case study is the STHORM accelerator, a clustered many-core architecture comprising dual-instruction issue processors, a complex memory hierarchy and DMA engines. Experimental results show that we can perform fast power estimations with an estimation error lower than 4% for the VLIW cores, which are the main source of power consumption, and less than 10% for the overall SoC platform, and for a simulation time overhead lower than 1%.