Area optimized FPGA implementation of color edge detection

A new area optimized VLSI architecture for color edge detection using Sobel operator is designed and implemented on Virtex-5 FPGA Platform. The proposed architecture uses only one processing element for computing gradients for all three R, G, and B color components and aims at reducing the FPGA resources usages. The FPGA resource usage is reduced more than 35% as compared to standard implementation which uses three gradient computation blocks. The system can robustly detect color edges at a frame rate of 50 frames per second (fps) for standard PAL (720×576) size video.