Implementation of high speed energy efficient 4-bit binary CLA based incrementer decrementer

The paper presents the implementation of a high speed energy efficient 4-bit binary CLA based incrementer decrementer. The design methodology is extensively based on static CMOS logic and transmission gate logic to achieve higher operating frequencies, smaller delays and optimized area. This circuit is especially suitable for long bit incrementer/decrementer that can be used in program counter, frequency dividers and address generation unit in microprocessors. Simulation results illustrates that the designed adder has superior performance compared to existing adders in terms of power dissipation and speed. The proposed circuit is implemented on TSMC 0.18μm process model. The measurement results indicate that the proposed 4-bit incrementer/decrementer can operate up to 5GHz with 200x×160 μm
²
optimized area.