A 1Gb/s reconfigurable pulse compression radar signal processor in 90nm CMOS

This paper presents a reconfigurable analog signal processing circuit for pulse compression radar. Adapting bandwidth for the range of the target is proposed for radar systems. The baseband signal processor includes a high-speed correlator/integrator, a 4-bit flash analog-to-digital converter (ADC) and a multi-range delay lock loop (DLL). The DLL generates multi-phase clock to align the template signal with the received signal. The circuit is fabricated in 90-nm CMOS and can be configured to work from 50Mb/s to 1Gb/s with Barker codes. A sidelobe reduction (SLR) of 15.6dB is demonstrated for 1Gb/s. The total power consumption is 33mW at 1Gb/s.