Influence of TEOS/Si3N4 passivation layer on the performance of MOSFET/ISFET structure

This paper presents an investigation of dual passivation layer deposition on the characteristic of MOSFET/ISFET structure. PECVD TEOS oxide and LPCVD Silicon nitride (Si3N4) has been used as the passivation layer and deposited on the metal shield layer of ISFET. The Keithley 236 Parameter Analyzer and Semi-auto prober micromanipulator system was used to measure the drain-source current (IDS) versus gate to source voltage (VGS) characteristics. In this study, unpassivated and passivated structure were characterized and compared. The negative shift of threshold voltage, VTH is observed after passivation layer was deposited. This might be due to the charge trapping of electrons or deposition process of passivation layer.