A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS

Constructed from a current reused architecture for low power consumption, a cascode topology of an LC VCO and a divide-by-4 prescaler is used in a PLL. In the prescaler, the first-stage divide-by-2 divider is an injection locking circuit used to frequency lock to an incident signal to perform frequency division. The next-stage divide-by-2 divider uses the conventional D-type filpflop with optimizing the threshold voltage to lower the operating voltage. Implemented with 1.8-V 0.18-μm CMOS, the PLL provides the phase noise of -121.67 dBc/Hz at 1-MHz offset and consumes 3.4 mW at 2.4 GHz.