Physical implementation, parasitic extraction and parameter comparison of LNA with two types of ESD protection structures

The paper presents an equivalent circuit of LNA with different ESD protection structures, which are used to discharge the excess power. The two different circuits are physically implemented and extracted in 0.18μm CMOS technology. The goal is to realize LNA with ESD protection and to run post extract simulations, to see how parasitic elements influences of the LNA's work under certain conditions. The simulation results are compared and analyzed for two different types ESD protection structures. For presented circuit models in this work CADANCE design system is used.