Global routing congestion reduction with cost allocation look-ahead

This work presents two techniques to define and treat areas that have high interconnection demand in the design of VLSI circuits, during global routing. These techniques are applied in two steps over all global routing flow. The first technique is executed in the pre-routing phase, where are identified regions with a high interconnection density, (there is a large number of sources or destinations reducing its ability to allocate interconnections); the second technique is applied in the iterative routing phase, identifying and protecting those regions from having high congestion, by cost pre-allocation techniques. Three cost pre-allocation parameters were identified and their values are defined on-the-fly, by functions, described in this paper. These techniques were included in an existing global routing flow, called GR-WL, to validate the impact of its implementation, through the extraction of three global routing metrics: wirelength, total value of maximum overflow (TOF) and maximum obtained overflow (MOF). By running experiments using these techniques, total congestion reduction was up to 16%. The results are more relevant when using benchmark circuits for which there is still no valid solutions in the literature. Furthermore, the running times achieved were up to 30% faster when compared to the reference implementation, with a maximum impact of 1.39% in the total wirelength.