Adaptive Equalizer Training for High-Speed Low-Power Communication Systems

In high-speed communication systems, adaptive equalizers are widely applied to improve signal integrity in both master chip and slave chip. In this paper, a novel architecture with the equalizers applied only in the master chip is proposed for the low-power design through adaptive equalizer training. The system architecture is verified by implementing the receiver equalizer training at the circuit level and the transmitter equalizer training using different algorithms: 1) direct calculation 2) LMS algorithm 3) pilot signal/peak detection in Matlab/Simulink. Results show that LMS algorithm improves the vertical and horizontal eye opening by more than 30% and 10%, respectively. Furthermore, the proposed architecture can achieve 411mW per channel, which is a two-fold reduction in the power dissipation with respect to the conventional architecture. To adapt the concept, Graphic DDR5 is taken as a study case.