A 6.25-Gbps 4-tap low-power decision feedback equalizer in 0.13µm CMOS technology

A half-rate 4-tap decision feedback equalizer (DFE) is implemented in 0.13μm CMOS technology for low-power I/O links. Modified current-mode logic (CML) latches with PMOS loads are used in the new proposed DFE to achieve better power and area efficiency. The proposed DFE consumes only 1.914mW from a 1.2V supply when equalizing 6.25Gb/s data passing through a simulated low-pass channel with 18 dB of loss at 3.125 GHz, which is 39.5% lower than the traditional design with resistor loaded CML latches.