Vertical nanowire MOSFET parasitic resistance modeling

In this work, the parasitic resistance components of Vertical nanowire FET (VNW) are analytically modeled considering the gate and device asymmetry. Further the models are used to analyze the scaling performance with varying channel length and source-drain extension length. The top and bottom electrode asymmetry leads to asymmetric parasitic resistances which determine gate overdrive or device current and the circuit delay. Thus the models can be used to optimize and quantify the VNW device performance.