A 3-transistor CMOS active pixel with in-pixel correlated double sampling

This paper presents a 3-transistor CMOS active pixel structure with in-pixel correlated double sampling. Designed in a standard 0.18 μm CMOS process, the structure effectively suppresses temporal noise and fixed pattern noise (FPN), thanks to the shared correlated double sampling circuit inside the pixel. Fill factor is also improved while maintaining pixel performance. Validation by Spectre simulator shows that the proposed structure suppresses 100 mV input offset to the microvolt range, and the pixel readout time is ~90 ns. The average power consumption of each pixel is 18 μW.