Design of an efficient high-speed VLSI architecture for WLAN modem

This paper proposes an architecture for the high-speed WLAN modem ASIC chip. The architecture supports the DS-SS physical layer specifications in the IEEE 802.11. The spread sequence can be extended up to 16 chips, the number of samples per chip is 2, and the maximum data rate is 4 Mbps. The proposed modem supports various data rates, i.e., 4 Mbps, 2 Mbps and 1 Mbps and provides DBPSK and DQPSK for data modulation. We have simulated algorithm models using the SPW/sup TM/ and verified the BER performance in AWGN channel environments and the carrier frequency offset and clock offset environments. The proposed architecture shows lower BER than the Harris HSP3824. The proposed modem chip is being fabricated using the Samsung/sup TM/ 0.6 /spl mu/m gate array library.