VHDL 200x-requirements from testbench-view

Both requirements for VHDL and restrictions to VHDL standards have been discussed by many groups and forums. A problem to be solved is to handle the growing complexity of hardware designs and test environments. The aim of the paper is to support the discussion by defining requirements impacted by modern verification techniques. We focus on the performance and modeling aspects from the testbench development view. Therefore we consider simulation methodologies, coding styles and in particular VHDL extensions. Further, the impact on VHDL extensions by modern requirements engineering methodologies are dealt with.