Error resilient logic circuits under dynamic variations

The design of low power and robust circuits under dynamic variations has emerged as a key challenge for silicon technologies. A particularly challenging problem is to tolerate transient supply noise that can occur in nanoseconds to microseconds time scales. The use of voltage or timing safety margin helps tolerate dynamic variations but at the expense of reduced performance or increased power dissipation. This talk will present adaptive circuit techniques to design resilient pipelines under fast transient variations. The presented techniques will allow a pipeline circuit to operate with minimal safety margin while preventing timing errors by adaptive clocking as well as time-borrowing and clock stretching. The measurement data from test-chips designed in 130nm CMOS technology will be presented to demonstrate the effectiveness of adaptive circuit techniques in designing low-power and resilient pipeline circuits.