Defect modelling and testability analysis of BiCMOS circuits

BiCMOS is a recent integrated circuit technology that is rapidly becoming a mainstream technology supporting high-speed applications. Highly complex circuits are now realizable with such a technology, which merges bipolar and MOS devices on a single substrate. Their fabrication process involves a mix of bipolar and MOS devices. These circuits must be tested to ensure that they have been processed correctly. This paper addresses the testability of BiCMOS circuits compared to equivalent CMOS circuits. Defects are modelled and their impacts on the behaviour of the circuits are analyzed by simulation. Faults are classified as logical faults or performance degradation faults. It is determined that BiCMOS gates are more difficult to test than the corresponding CMOS gates. Adequate fault models must therefore be constructed to improve the testability of BiCMOS circuits.