Gate-Stack Engineering in n-Type Ultrascaled Si Nanowire Field-Effect Transistors

The electrical properties of gate-stacks composed of an interfacial SiO_x layer and different types of high-κ dielectrics are theoretically investigated for potential applications as oxide layers in ultrascaled Si nanowire field-effect transistors with a gate length of 5 nm. As a simulation tool, a 3-D quantum transport solver based on the effective mass approximation and including gate leakage currents is employed. We determine how the dielectric constant of the high-κ layer and its conduction band offset with Si must be engineered so that an equivalent oxide thickness of 0.5-0.6 nm can be achieved while maintaining the transistor OFF-state current <;0.1 μA/μm.