Serial and parallel implementation of CORDIC architecture: A comparative approach

Many hardware efficient algorithms exist for hardware signal processing architecture. Among these algorithm there is a set of shift-add algorithms collectively known as CORDIC (Coordinate Rotation for Digital Computers) for computing a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. The paper compares the serial and parallel implementations of CORDIC architecture [1] with respect to their speed and device utilization. Both the implementations were done in Verilog, simulated using Modelsim simulator and Implemented in Xilinx FPGA synthesis on Spartan-3. [3]. In Parallel structure of CORDIC algorithm, with 31 iterations plus a PRELOAD cycle, the algorithm will take 32 clock cycles to complete. At the theoretical maximum clock frequency of 56.507 MHz, the unit will take 17.697 ns to compute the final value. A truly complete general unit that is capable of operating in all three domains in both modes should be possible with only a little more hardware.